In one of structures of solid-state imaging devices, a charge storage section (or memory) is interposed between a photodiode and a CCD section to temporarily store charges. In an image sensor provided with the charge storage section, since a dark current increases in proportion to a time period for which the charges are held in the charge storage section, image degradation becomes more remarkable in a case of storing the charges for a longer time period. Also, the dark current is almost doubled in the temperature rise by 8 to 10° C. Because of the above reasons, in the solid-state imaging device having the charge storage section, a method is adopted of applying a negative voltage to a gate electrode arranged above the charge storage section so that the interface between a gate oxide film and a silicon substrate is pinned to a ground potential, to suppress the dark current due to interface levels (e.g. Patent Literature 1).
Patent literature 1 discloses a technique relating to a solid-state imaging device in which signal charges can be held for an optionally controlled light reception time and the signal charges can be transferred without generation of afterimages while suppressing generation of a dark current.
FIG. 1A is a cross sectional view of a solid-state imaging device 100 disclosed in Patent Literature 1. FIG. 1B is a diagram showing a transition state of potential wells in a depth direction. A solid line and a broken line in FIG. 1B indicate a transition of a potential level depending on a voltage applied to each electrode. The solid-state imaging device 100 has a charge transfer gate section 102 interposed between a photoelectric conversion section (i.e. photodiode) 101 and a charge storage section 103. Also, a charge transfer gate section 104 is interposed between the charge storage section 103 and a CCD section 105. An n-type diffusion layer 112 with the impurity concentration of n1 is arranged in a p-type semiconductor substrate 118 and a p+-type diffusion layer 113 is arranged on the n-type diffusion layer 112. These diffusion layers constitute the photoelectric conversion section (or photodiode) 101 in the solid-state imaging device 100.
An n-type diffusion layer 111 (with the impurity concentration of n) is arranged in a range from the charge transfer gate section 102 to the CCD section 105. A p-type diffusion layer 114 with the impurity concentration of p1 is arranged under a charge transfer gate electrode 106. A p-type diffusion layer 116 with the impurity concentration of p2 is arranged under a charge transfer gate electrode 108. On outer sides of the photoelectric conversion section (or photodiode) 101 and the CCD section 105, a p+-type diffusion layer 110 and a p+-type diffusion layer 117 are respectively arranged for element isolation. A drive pulse •TG1 is applied to the charge transfer gate electrode 106, a drive pulse •TG2 is applied to the charge transfer gate electrode 108, a drive pulse •1 is applied to a CCD section gate electrode 109, and a DC voltage V2 is applied to a charge storage gate electrode 107. Also, in general, the p-type semiconductor substrate 118 is connected to the ground potential (not shown).
Charges stored in the photoelectric conversion section (or photodiode) 101 are transferred to a region under the charge storage gate electrode 107 when the drive pulse •TG1 is turned on and the drive pulse •TG2 is turned off. After the transfer is completed, the drive pulse •TG1 is turned off. Next, after temporarily storing the charges in the charge storage section 103, the drive pulse •TG2 is turned on and the drive pulse •1 is further turned on, so as to transfer the stored charges to the CCD section 105. After completion of the transfer, the drive pulse •TG2 is turned off. Thereafter, the charges stored in the CCD section 105 are transferred to an output amplifier (not shown) by a pulse-driving technique.
Because the n-type diffusion layer 111 with the impurity concentration of n is formed in a range from the photoelectric conversion section (or photodiode) 101 to the CCD section 105, a so-called embedded channel is produced in which a charge transfer path is not provided on a Si surface. An upper portion of FIG. 2 shows a cross section of the charge storage section 103 along the line C-C′ in FIG. 1A. A lower portion of FIG. 2 is a diagram showing a potential distribution in a depth direction of the cross section. A negative voltage equal to or less than a pinning start voltage is applied to the charge storage gate electrode 107. An interface between the n-type diffusion layer 111 with the impurity concentration of n and a gate oxide film 119 is set to the ground (GND) potential, like of the p-type semiconductor substrate 118. Therefore, generation of a dark current due to interface levels is suppressed.
According to the trend of resolution improvement in an image sensor in recent years, a pixel pitch is shortened greatly and a channel width in a charge storage section is also narrowed. Because characteristics such as sensitivity and a saturation charge amount are maintained to a certain degree through structural improvement of photodiode and area extension even if the pixel pitch is shortened, the charge storage section needs to have an adequate charge storage capacity. Accordingly, it is necessary to extend the charge storage section into a transfer direction, and it sometimes causes a problem of degradation of charge transfer efficiency. A technique to improve charge transfer efficiency is known by Patent Literature 2, for example.
Patent Literature 2 discloses a technique for improving signal charge transfer speed by changing a length of a transfer electrode and dividing a channel section disposed under a longer transfer electrode, into regions having different impurity concentrations. The technique according to Patent Literature 2 realizes under a constant transfer frequency, reduction of transfer remainder of the signal charges and improvement of transfer quality. The technique according to Patent Literature 2 also makes it possible to increase the transfer frequency if the transfer is carried out with the same quality.
FIGS. 3A and 3B are diagrams showing a schematic structure of a solid-state imaging device according to Patent Literature 2. FIG. 3A is a cross sectional view showing a solid-state imaging device 200. FIG. 3B shows a potential diagram under each gate electrode in the cross section. A solid line and a broken line in FIG. 3B show a transition state of a potential distribution according to a voltage applied to each electrode. Referring to FIG. 3A, in a p-type semiconductor substrate 133 of the solid-state imaging device 200, an n-type diffusion layer 132 with the impurity concentration of n− is arranged. Under each of a second-layer gate electrode 128 and a second-layer gate electrode 130, an n-type diffusion layer 131 with the impurity concentration of n is arranged. Therefore, a so-called embedded channel is generated in which a charge transfer path does not pass through a Si surface. A first-layer gate electrode 127, a first-layer gate electrode 129, the second-layer gate electrode 128 and the second-layer gate electrode 130 are arranged on a main surface of the silicon substrate through a gate oxide film. A drive pulse •4, a drive pulse •2, a drive pulse •1 and a drive pulse •3 are applied to the gate electrodes, respectively, for the purpose of charge transfer.
The n-type diffusion layer 131 is arranged partially under the second-layer gate electrode 128 and the second-layer gate electrode 130. Thus, as shown in FIG. 3B, a channel potential difference is generated under the same gate electrode, to strengthen a transfer electric field, resulting in improvement of charge transfer efficiency.
Citation List:
[Patent Literature 1]: JP 2008-258571A
[Patent Literature 2]: Japanese Patent No. 3366656